1. Field of the Invention
This invention relates generally to semiconductor fabrication technology, and, more particularly, to a method of lowering and/or reducing the Miller capacitance at the edges of a structure such as a gate structure of a metal oxide semiconductor field effect transistor (MOSFET or MOS transistor).
2. Description of the Related Art
There is a constant drive within the semiconductor industry to increase the operating speed of integrated circuit devices, e.g., microprocessors, memory devices, and the like. This drive is fueled by consumer demands for computers and electronic devices that operate at increasingly greater speeds. This demand for increased speed has resulted in a continual reduction in the size of semiconductor devices, e.g., transistors. That is, many components of a typical field effect transistor (FET), e.g., channel length, junction depths, gate dielectric thickness, and the like, are reduced. For example, all other things being equal, the smaller the channel length of the FET, the faster the transistor will operate. Thus, there is a constant drive to reduce the size, or scale, of the components of a typical transistor to increase the overall speed of the transistor, as well as integrated circuit devices incorporating such transistors. Additionally, reducing the size, or scale, of the components of a typical transistor also increases the density and number of the transistors that can be produced on a given amount of wafer real estate, lowering the overall cost per transistor as well as the cost of integrated circuit devices incorporating such transistors.
However, reducing the channel length of a transistor also increases xe2x80x9cshort-channelxe2x80x9d effects, almost by definition, as well as xe2x80x9cedge effectsxe2x80x9d that are relatively unimportant in long channel transistors. Short-channel effects include, among other things, an increased drain-source leakage current when the transistor is supposed to be switched xe2x80x9coff,xe2x80x9d believed to be due to an enlarged depletion region relative to the shorter channel length. One of the edge effects that may influence transistor performance is known as Miller capacitance. The Miller capacitance is an overlap capacitance that arises because the conductive doped-polycrystalline silicon (doped-poly) gate almost invariably overlaps, with a conductive portion of either the more heavily-doped source/drain regions or the less heavily-doped source/drain extension (SDE) regions, if present, of a conventional metal oxide semiconductor field effect transistor (MOSFET or MOS transistor).
As shown in FIG. 1, for example, a conventional MOS transistor 100 may be formed on a semiconducting substrate 105, such as doped-silicon. The MOS transistor 100 may have an N+-doped-poly (P+-doped-poly) gate 110 formed above a gate oxide 115 formed above the semiconducting substrate 105. The N+-doped-poly (P+-doped-poly) gate 110 and the gate oxide 115 may be separated from N+-doped (P+-doped) source/drain regions 120S and 120D of the MOS transistor 100 by dielectric spacers 125. The dielectric spacers 125 may be formed above N+-doped (P+-doped) source/drain extension (SDE) regions 130S and 130D. As shown in FIG. 1, shallow trench isolation (STI) regions 140 may be provided to isolate the MOS transistor 100 electrically from neighboring semiconductor devices such as other MOS transistors (not shown).
The Nxe2x88x92-doped (Pxe2x88x92-doped) SDE regions 130S and 130D are typically provided to reduce the magnitude of the maximum channel electric field found close to the N+-doped (P+-doped) source/drain regions 120S and 120D of the MOS transistor 100, and, thereby, to reduce the associated hot-carrier effects. The lower (or lighter) doping the Nxe2x88x92-doped (Pxe2x88x92-doped) SDE regions 130S and 130D, relative to the N+-doped doped) source/drain regions 120S and 120D of the MOS transistor 100 (lower or lighter by at least a factor of two or three), reduces the magnitude of the maximum channel electric field found close to the N+-doped (P+-doped) source/drain regions 120S and 120D of the MOS transistor 100, but increases the source-to-drain resistances of the Nxe2x88x92-doped (Pxe2x88x92-doped) SDE regions 130S and 130D.
As shown in FIG. 1, typically there are overlap regions 135S and 135D (indicated in phantom) where the edges of the N+-doped-poly (P+-doped-poly) gate 110 overlap with the edges of the Nxe2x88x92-doped (Pxe2x88x92-doped) SDE regions 130S and 130D, respectively. The typical amount of overlap xcex94 in each of the overlap regions 135S and 135D, as shown in FIG. 1, may be about 200 xc3x85, for example. As the overall dimensions of the MOS transistor 100 are reduced, the Miller capacitance becomes more of a dominant factor, particularly affecting the switching speed of the MOS transistor 100.
The drain overlap region 135D gives rise to the Miller capacitance, since the N+-doped (P+-doped) source region 120S is typically grounded and the voltage is usually applied to the N+-doped (P+-doped) drain region 120D to drive the source-to-drain current. Generally, the Miller capacitance refers to the capacitance between two terminals switching in opposite directions. For example, when the MOS transistor 100 is in an xe2x80x9coffxe2x80x9d state, there may be some residual charge (electrons, for an N-channel MOS transistor 100, and holes, for a P-chancel MOS transistor 100) stored in the drain overlap region 135D, primarily due to the Miller capacitance. This xe2x80x9cMiller chargexe2x80x9d must be discharged before the MOS transistor 100 may be switched from the xe2x80x9coffxe2x80x9d state to an xe2x80x9conxe2x80x9d state, slowing down the switching speed. Similarly, the Miller capacitance in the overlap region 135D must be charged up again with the xe2x80x9cMiller chargexe2x80x9d after the MOS transistor 100 is switched from the xe2x80x9conxe2x80x9d state to the xe2x80x9coffxe2x80x9d state, further slowing down the switching speed. When an N-channel MOS transistor 100 is in an xe2x80x9coffxe2x80x9d state, the voltage of the N+-doped-poly gate 110 may be in a xe2x80x9clowxe2x80x9d or xe2x80x9c0xe2x80x9d state and the voltage of the N+-doped drain region 120D, and, hence the Nxe2x88x92-doped SDE region 130D, may be in a xe2x80x9chighxe2x80x9d or xe2x80x9c1xe2x80x9d state. When the N-channel MOS transistor l00 is then switched to an xe2x80x9conxe2x80x9d state, the voltage of the N+-doped-poly gate 110 may go to a xe2x80x9chighxe2x80x9d or xe2x80x9c1xe2x80x9d state and the voltage of the N+-doped drain region 120D, and, hence the Nxe2x88x92-doped SDE region 130D, may go to a xe2x80x9clowxe2x80x9d or xe2x80x9c0xe2x80x9d state (toward the xe2x80x9clowxe2x80x9d or xe2x80x9c0xe2x80x9d or grounded state of the N+-doped source region 120S), as electrons flow in the source-to-drain direction through an inverted N-channel formed in the otherwise p-type semiconducting substrate 105. The N+-doped-poly gate 110 and the Nxe2x88x92-doped SDE region 130D are capacitively coupled by the overlap capacitance (Miller capacitance) to the drain overlap region 135D. This overlap capacitance (Miller capacitance) in the drain overlap region 135D tends to resist the switching of the N-channel MOS transistor 100.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.
In one aspect of the present invention, a method is provided, the method including forming a gate dielectric above a surface of the substrate and forming a doped-poly gate structure above the gate dielectric, the doped-poly gate structure having an edge region. The method also includes forming a dopant-depleted-poly region in the edge region of the doped-poly gate structure adjacent the gate dielectric.
In another aspect of the present invention, an MOS transistor having a reduced Millet capacitance is provided, the MOS transistor formed by a method including forming a gate dielectric above a surface of the substrate and forming a doped-poly gate structure above the gate dielectric, the doped-poly gate structure having an edge region. The method also includes forming a dopant-depleted-poly region in the edge region of the doped-poly gate structure adjacent the gate dielectric.
In yet another aspect of the present invention, an MOS transistor is provided, the MOS transistor including a gate dielectric above a surface of a substrate and a doped-poly gate structure above the gate dielectric, the doped-poly gate structure having an edge and an edge region. The MOS transistor also includes a dopant-depleted-poly region in the edge region of the doped-poly gate structure adjacent the gate dielectric.